HANDS-ON SIMULATION · LEARN BY DOING

Interactive Laboratories & Visualizers

Step-by-step interactive concept simulators embedded directly into the course curriculum. Experiment with scheduling parameters, memory allocations, precedence graphs, and indexing trees in real time.

ACTIVE SUBJECTS:Operating Systems (8 Labs)DBMS (3 Labs)COA (In Development)Digital Logic (In Development)Computer Networks (In Development)
LAB 01 · Module 5: DeadlocksInteractive

Banker's Algorithm Safe State & Sequence Finder

Interactive multi-resource matrix calculator. Dynamically adjust Allocation, Max, and Available vectors to trace safe sequences and detect deadlock-prone unsafe states step-by-step.

✓Matrix computation
✓Step-by-step execution
✓Deadlock trap check
Deadlock AvoidanceSafe State
Launch Lab→
LAB 02 · Module 3: CPU SchedulingInteractive

CPU Scheduling Gantt Chart & Metrics Simulator

Simulate FCFS, SJF (Preemptive/Non-preemptive), and Round Robin with adjustable time quanta. Visualizes the Gantt chart, ready queue, and computes exact average Waiting Time (WT) and Turnaround Time (TAT).

✓Interactive time quantum
✓Animated Gantt chart
✓Average metric breakdown
Round RobinSJF/SRTF
Launch Lab→
LAB 03 · Module 2: Processes & ConcurrencyInteractive

5-State vs 7-State Process Lifecycle Machine

Explore process transitions between New, Ready, Running, Waiting, Terminated, Suspend-Ready, and Suspend-Blocked. Traces memory swapping between RAM and swap space.

✓State transition machine
✓Swap space visualizer
✓Event trigger testing
State TransitionsSuspend-Ready
Launch Lab→
LAB 04 · Module 1: OS FoundationsInteractive

Dual-Mode Execution & System Call Boundary Visualizer

Step through the hardware mode bit transition (0 for kernel mode, 1 for user mode), trap instruction issuance, interrupt vector table (IVT) indexing, and safe return to user space.

✓Hardware mode bit toggle
✓Register preservation
✓Ring 0 vs Ring 3
Mode BitTrap Instruction
Launch Lab→
LAB 05 · Module 7: Virtual MemoryInteractive

Page Replacement Simulator (FIFO, LRU, Optimal)

Simulate page fault rates across FIFO, Least Recently Used (LRU), and Optimal algorithms on custom reference strings. Directly verify Belady's Anomaly by changing frame counts.

✓Reference string input
✓Frame size adjustment
✓Page hit/miss telemetry
FIFO vs LRU vs OptimalBelady's Anomaly
Launch Lab→
LAB 06 · Module 9: I/O & StorageInteractive

Disk Head Trajectory & Seek Distance Simulator

Trace mechanical arm movement across disk cylinders for FCFS, SSTF, SCAN, C-SCAN, and LOOK algorithms. Calculates total cylinder seek distance and boundary turnaround points.

✓Cylinder trajectory plotting
✓Seek distance calculation
✓Algorithm comparison
SCAN / C-SCANSSTF Seek Time
Launch Lab→
LAB 07 · Module 4: ConcurrencyInteractive

Counting & Binary Semaphore Resource Tracker

Visualizes the wait queue and value changes for P(S) and V(S) operations. Demonstrates how semaphores maintain mutual exclusion and prevent race conditions in critical sections.

✓Wait / Signal operations
✓Queue blockage simulation
✓Bounded buffer testing
SemaphoresMutual Exclusion
Launch Lab→
LAB 08 · Module 2: Processes & ConcurrencyInteractive

Context Switching PCB Snapshot Visualizer

Shows how the operating system saves process registers, program counter, and stack pointers into the Process Control Block (PCB) before restoring the next ready process.

✓PCB memory layout
✓Switch overhead timeline
✓Hardware state preservation
Process Control BlockContext Switch Cost
Launch Lab→
LAB 09 · Module 7: Transactions & ConcurrencyInteractive

Precedence Graph & Conflict Serializability Checker

Interactive conflict serializability analyzer. Detects conflicting read/write pairs across concurrent transactions, builds the directed precedence graph, spots cycles, and computes the equivalent topological serial schedule.

✓Interactive schedule presets
✓Real-time conflicting pair detection
✓Cycle isolation & topological sort
Conflict SerializabilityPrecedence Graph
Launch Lab→
LAB 010 · Module 6: Storage & IndexingInteractive

B+ Tree Node Order, Capacity & Height Calculator

Solve the exact algebraic inequalities for internal node order p and leaf node order m based on block, key, and pointer sizes. Estimates tree height and disk block I/O accesses for tables.

✓Internal order inequality solver
✓Leaf order inequality solver
✓Multi-level table capacity estimator
B+ Tree OrdersBlock Inequality
Launch Lab→
LAB 011 · Module 5: NormalizationInteractive

Functional Dependency, Candidate Key & Normalization Engine

Interactive relational schema evaluator. Compute live attribute closures (X+), derive all minimal candidate keys, and check relations against 1NF, 2NF, 3NF, and BCNF with violation callouts.

✓Live attribute closure calculator
✓Minimal candidate key generator
✓Normal form evaluation breakdown
Attribute ClosureCandidate Keys
Launch Lab→