Computer Organization & Architecture
“Master instruction formats, addressing modes, IEEE 754 floats, Booth's multiplication, cache mapping, AMAT, 5-stage pipelining hazards, microprogramming, and DMA.”
A rigorous, mathematically precise study notebook covering the internal architecture and operational hardware of modern computing systems: machine instructions, addressing modes, expanding opcodes, datapath timing, IEEE 754 floating-point standard, Booth's multiplication, restoring/non-restoring division, cache bit-splitting, multi-level AMAT, 5-stage RISC instruction pipelining, RAW hazard forwarding, branch penalties, hardwired and microprogrammed control units, and interrupt/DMA I/O transfer for undergraduate excellence and top-rank GATE CS/IT performance.
Structured Notes & Exam Lens
A · B.Tech Structured Study Sequence
5 Sections · Full CurriculumMachine Instructions, Addressing Modes & Datapath
Instruction cycle state transitions, 0/1/2/3-address instruction formats, expanding opcode formulations, effective address computation across all classical addressing modes, and single/multi-cycle datapath execution delays.
EA calculations, memory reference counting, opcode expansion, and addressing modes.
Single-cycle vs multi-cycle datapath delays, RTL register transfers, and ALU flags.
Computer Arithmetic, IEEE 754 & Booth's Algorithm
Signed 2's complement arithmetic, ALU overflow flags, Booth's multiplication recoding, restoring and non-restoring division, and IEEE 754 single/double precision floating-point standard.
Single/Double precision layouts, subnormal values, and Booth bit-pair recoding.
Binary restoring/non-restoring division cycles and CLA propagation-generation gate delays.
Memory Hierarchy, Cache Mapping & AMAT
Direct-mapped, fully associative, and k-way set-associative cache bit splitting, tag directory sizing, Average Memory Access Time (AMAT), write-through/write-back policies, and memory interleaving.
Tag/Index/Offset bit splitting, multi-level cache AMAT, and tag directory overhead.
Write-through vs write-back, write allocate, LRU stacks, and memory interleaving math.
Instruction Pipelining, Hazards & Performance
5-stage RISC pipeline, clock cycle time = max(stage) + latch, speedup formulas, RAW/WAR/WAW data hazards, operand forwarding bypassing paths, and branch penalties.
Clock period = max(stage) + latch, RAW data stalls, forwarding, and speedup.
Branch penalties, 2-bit saturating counters, Branch Target Buffers (BTB), and delayed branch.
Control Unit Design, DMA & Interrupts
Hardwired vs microprogrammed control units, horizontal vs vertical microinstructions, control store sizing, programmed I/O, interrupts, and DMA transfer modes.
Horizontal/Vertical control words, control store sizing, and DMA cycle stealing.
Vectored vs non-vectored interrupts, daisy chaining propagation delay, and bus arbitration.
B · GATE 2027 Syllabus Scope
Official syllabus scope and related lesson coverage; topics outside the syllabus are marked as enrichment.
- •Machine instructions and addressing modes: Instruction formats (0, 1, 2, 3 address), instruction cycle, addressing modes, expanding opcodes, RISC vs CISC
- •ALU, data-path and control unit: Single-cycle and multi-cycle datapaths, fixed and floating point arithmetic, Booth's algorithm, division, hardwired and microprogrammed control
- •Instruction pipelining: Pipeline hazards (structural, data, control), operand forwarding, branch prediction, pipeline performance, speedup and CPI
- •Memory hierarchy: Cache memory mapping (direct, associative, set-associative), cache lines, replacement policies, write policies, AMAT, memory interleaving
- •I/O interface: Interrupts (vectored, priority, daisy chaining), DMA (cycle stealing, burst transfer, transparent)
Interactive Labs & Verified PYQs
Revision & Rapid Review Sheets
Authoritative Textbooks & Video Lectures
All notes in this notebook cross-reference standard academic literature. We do not pretend student notes substitute for classical texts — they guide you through them.
Curated lectures from verified educators (Gate Smashers, Neso Academy, Knowledge Gate, and MIT OCW) selected specifically for difficult concept visualizations.
These notes are open and maintained together.
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