Cache Replacement, Write Policies & Memory Interleaving

When the CPU writes data to memory, cache and main memory must maintain consistency:

1. Write-Hit Policies:

- Write-Through: Every write to the cache is simultaneously propagated to main memory. Main memory is always up to date. Requires a Write Buffer to avoid CPU stalling during slow RAM writes.

- Write-Back (Copy-Back): Data is written only to the cache line. The block is written back to main memory ONLY when it is evicted. Requires a Dirty Bit (Modified Bit) per cache line to track if the line was modified.

2. Write-Miss Policies:

- Write-Allocate (Fetch on Write): The block is loaded into the cache from main memory on a write miss, followed by the write hit operation. Usually paired with Write-Back.

- No-Write-Allocate (Write Around): The block is modified directly in main memory without loading it into the cache. Usually paired with Write-Through.

3. Main Memory Interleaving:

Divides physical memory into m independent banks to achieve concurrent memory accesses:

- High-Order Interleaving: Most significant bits select the memory bank; lower bits select the word within the bank. Does NOT provide parallelism for sequential array accesses.

- Low-Order Interleaving: Least significant bits select the memory bank (Bank = Address \bmod m). Consecutive addresses fall into consecutive memory banks! Allows pipelined access of m consecutive words in time T + (m - 1) × t_{bus}.