DIGITAL LOGIC/Student Engineering Notebook
Page 03·notes
NUMBER REPRESENTATION & COMPUTER ARITHMETIC CIRCUITS—~28 MIN READ

Signed Number Representations, 2's Complement & Overflow Arithmetic

“Range boundaries, sign extension rules, modular arithmetic, and two's complement overflow detection.”

1.The Hardware Elegance of 2's Complement

Computer hardware overwhelmingly uses 2's complement for signed integer arithmetic because it allows addition and subtraction to be executed by identical adder hardware without sign-checking logic.

Weight of the MSB: In an n-bit 2's complement number A = a_{n-1} a_{n-2} ... a_1 a_0, the MSB has a negative weight: Value(A) = -a_{n-1} 2^{n-1} + \sum_{i=0}^{n-2} a_i 2^i.

Arithmetic Overflow: Because finite-word registers have bounded ranges, adding two large positive numbers can produce a negative result (sign bit becomes 1), or adding two large negative numbers can produce a positive result (sign bit becomes 0).

Hardware Overflow Detection: In an n-bit adder with carry-in C_{n-1} into the sign bit and carry-out C_n out of the sign bit, overflow occurs if and only if V = C_n \oplus C_{n-1} = 1. A simple XOR gate on the final two carry lines detects overflow in a single gate delay.

mental model— Carry Out vs Overflow

Carry-out (C_{out} = 1) indicates an unsigned overflow (result exceeds 2^n - 1). Overflow (V = 1) indicates a signed overflow (result outside [-2^{n-1}, 2^{n-1}-1]). They are completely independent conditions!

WORKED EXAM ANALYSIS · STEP-BY-STEP DERIVATION2 Marks (GATE CS)

2. Worked Analysis: 2's Complement Subtraction & Overflow

⚠️ Pitfall Warning:

Remember to sign-extend both operands to the same bit width before performing addition.

Problem Statement (Modeled on GATE Pattern):

Let A = 101100 and B = 100101 be two 6-bit 2's complement numbers.

Compute S = A - B in 6-bit 2's complement arithmetic and determine whether signed overflow occurs.

Step 1: Determine decimal values of A and B:

- A = 101100: MSB is 1 (negative). Value = -32 + 8 + 4 = -20.

- B = 100101: MSB is 1 (negative). Value = -32 + 4 + 1 = -27.

- Expected result: A - B = (-20) - (-27) = +7.

Step 2: Find 2's complement of B:

- B = 100101.

- Invert bits: 011010. Add 1: 011011 (+27).

Step 3: Compute A + (-B):

1 0 1 1 0 0 (A = -20)

+ 0 1 1 0 1 1 (-B = +27)

-------------

Carry bits: 1 1 1 0 0 0

Sum = (1) 0 0 0 1 1 1

- 6-bit result = 000111 (+7 in decimal).

Step 4: Check Overflow:

- Carry into MSB (C5) = 1.

- Carry out of MSB (C6) = 1.

- V = C6 XOR C5 = 1 XOR 1 = 0.

- No overflow! The result +7 is within the 6-bit signed range [-32, +31].

SOURCE TRANSPARENCY & CITATIONS

Primary Academic References & Exam Sources

Every concept in Notes From a B.Tech Brain is synthesized from authoritative academic texts, seminal peer-reviewed research, verified exam archives, and renowned university lectures.

Curated University Lecture Series
Computer Organization and Architecture (10th Edition) ·
LECTURE SERIES
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