Addressing Modes, Effective Address & Expanding Opcodes
“EA calculations, memory reference counting, opcode expansion, and addressing modes.”
1.The Classical Addressing Modes & Effective Address (EA)
§ 1.1.An addressing mode specifies how the processor's execution unit interprets or modifies an instruction's address field to locate the actual target operand in memory or registers. The computed memory location of the operand is called the Effective Address (EA).
Complete Classification of Addressing Modes & Memory Reference Costs:
1. Immediate Mode: The operand is embedded directly inside the instruction word (e.g., ADD R1, #42). EA = None. 0 memory references to fetch operand.
2. Register Mode: The operand resides in a named CPU register (e.g., ADD R1, R2). EA = Register address. 0 memory references.
3. Direct (Absolute) Mode: The instruction address field contains the actual main memory address of the operand (e.g., LOAD R1, [1000]). EA = Address field (A). 1 memory reference to read operand.
4. Indirect Mode: The address field points to a memory word that holds the effective address of the operand (e.g., LOAD R1, @[1000]). EA = Memory[A]. Requires 2 memory references (1 for pointer address + 1 for operand).
5. Register Indirect Mode: A CPU register holds the effective memory address (e.g., LOAD R1, (R2)). EA = [R2]. Requires 1 memory reference.
6. Indexed Mode: EA = Base Address (in instruction) + Index Register (IR). Used for sequential array element traversal (A[i]), where the index register holds the array subscript.
7. Base Register Mode: EA = Base Register (BR) + Displacement/Offset. Used for operating system program relocation; the base register points to the program segment origin in RAM.
8. Relative Mode (PC-Relative): EA = Program Counter (PC) + Offset. Crucial for position-independent conditional branches (BEQ target). If the branch is taken, the signed offset is added to the PC.
9. Auto-Increment / Auto-Decrement: EA = [R]; then R ← R + d (or R ← R - d; then EA = [R]). Essential for efficient hardware stack implementations and memory copy loops.
Always count the instruction fetch memory access in addition to operand accesses! For instance, an instruction ADD (R1) requires: 1 memory cycle to fetch instruction + 1 memory cycle to read operand at Memory[R1] = Total 2 memory access cycles. If the instruction word is 32 bits on a 16-bit memory bus, the instruction fetch alone requires 2 memory accesses!
2. GATE Worked Numerical: Expanding Opcode Formulation
Every unallocated pattern at an n-address level is multiplied by 2^k when expanded to the (n-1)-address level, where k is the bit-width of the freed register address field!
Problem: A processor has a 16-bit instruction word and 16 general-purpose CPU registers (requiring 4 bits each for register addressing). The processor supports 3-address, 2-address, and 1-address instructions.
If the instruction set architecture defines 14 three-address instructions and 30 two-address instructions, calculate the maximum number of 1-address instructions that can be supported.
Step 1: Bit allocation for 3-address format:
Instruction layout: [Opcode (4 bits)] [Reg1 (4 bits)] [Reg2 (4 bits)] [Reg3 (4 bits)].
Total possible opcode bit patterns with 4 bits = 2^4 = 16.
Step 2: Determine available patterns for 2-address expansion:
Used 3-address opcodes = 14.
Unassigned opcode prefixes = 16 - 14 = 2 prefixes.
Step 3: Bit allocation for 2-address format:
Instruction layout: [Prefix (4 bits)] [Expanded Opcode (4 bits)] [Reg1 (4 bits)] [Reg2 (4 bits)].
Each free prefix expands into 2^4 = 16 distinct 2-address instructions.
Total possible 2-address instructions = 2 * 16 = 32 instructions.
Used 2-address instructions = 30.
Remaining free prefixes for 1-address expansion = 32 - 30 = 2 prefixes.
Step 4: Bit allocation for 1-address format:
The next 4-bit register field is freed to expand the opcode.
Instruction layout: [2-address Prefix (8 bits)] [Expanded Opcode (4 bits)] [Reg1 (4 bits)].
Each of the 2 remaining free prefixes yields 2^4 = 16 distinct 1-address instructions.
Maximum 1-address instructions = 2 * 16 = 32 instructions.
Primary Academic References & Exam Sources
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