Instruction Cycle State Machine & Datapath Timing Analysis
“Single-cycle vs multi-cycle datapath delays, RTL register transfers, and ALU flags.”
1.The Classical Instruction Cycle & RTL Semantics
§ 1.1.Every machine instruction executes through a sequence of micro-operations coordinated by the central processor clock:
1. Fetch Cycle (IF):
- MAR ≤ftarrow PC
- MDR ≤ftarrow Memory[MAR], \quad PC ≤ftarrow PC + 4
- IR ≤ftarrow MDR
2. Decode Cycle (ID / RF):
- Decode opcode in IR, extract register specifiers, read source registers A ≤ftarrow R[rs], B ≤ftarrow R[rt], and sign-extend immediate constants.
3. Execute Cycle (EX):
- ALUOut ≤ftarrow A op B (arithmetic/logical instruction) or compute branch target address PC ≤ftarrow PC + offset.
4. Memory Access Cycle (MEM):
- For LOAD: MDR ≤ftarrow Memory[ALUOut].
- For STORE: Memory[ALUOut] ≤ftarrow B.
5. Write-Back Cycle (WB):
- R[rd] ≤ftarrow ALUOut (ALU operation) or R[rt] ≤ftarrow MDR (LOAD operation).
ALU Status Flags (Condition Codes):
- Zero Flag (Z): Set to 1 if the result is all zeros.
- Sign Flag (S / N): Equals the MSB of the result (1 for negative in 2's complement).
- Carry Flag (C): Set if an unsigned addition generates a carry out of the MSB, or an unsigned subtraction requires a borrow.
- Overflow Flag (V): Set if signed 2's complement addition/subtraction produces a result outside the representable range [-2^{n-1}, 2^{n-1}-1]. Formally: V = C_{in} \oplus C_{out} at the MSB position.
2. GATE Worked Numerical: Single-Cycle vs Multi-Cycle Datapath Delay
In a single-cycle datapath, the clock period MUST accommodate the SLOWEST instruction in the instruction set architecture (typically LOAD). In a multi-cycle datapath, the clock period equals the SLOWEST functional unit plus register setup time!
Problem: A processor has functional unit latencies: Instruction Memory = 250 ps, Register File Read = 150 ps, ALU = 200 ps, Data Memory = 300 ps, and Register File Write = 100 ps. Multiplexers and wiring introduce zero delay.
Compare the clock cycle time of:
1. A single-cycle datapath.
2. A multi-cycle datapath.
3. Calculate the execution time ratio for a program where 25% of instructions are LOAD (5 cycles), 10% are STORE (4 cycles), 50% are R-type (4 cycles), and 15% are BRANCH (3 cycles).
Step 1: Single-cycle clock period:
The longest instruction path is LOAD: Instruction Memory + Register Read + ALU + Data Memory + Register Write.
T_{single} = 250 + 150 + 200 + 300 + 100 = 1000 ps = 1.0 ns.
Every instruction must take exactly 1000 ps regardless of its type.
Step 2: Multi-cycle clock period:
T_{multi} = \max(250, 150, 200, 300, 100) = 300 ps (dictated by Data Memory).
Step 3: Average CPI for multi-cycle execution:
CPI_{multi} = (0.25 × 5) + (0.10 × 4) + (0.50 × 4) + (0.15 × 3)
CPI_{multi} = 1.25 + 0.40 + 2.00 + 0.45 = 4.10 cycles/instruction.
Step 4: Average time per instruction:
Single-cycle: 1 × 1000 ps = 1000 ps.
Multi-cycle: 4.10 × 300 ps = 1230 ps.
Single-cycle is 1230 / 1000 = 1.23× faster for this specific instruction mix, but multi-cycle allows hardware sharing (single memory and single ALU).
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