IEEE 754 Floating Point & Booth's Algorithm
“Single/Double precision layouts, subnormal values, and Booth bit-pair recoding.”
1.The IEEE 754 Floating-Point Standard (32-Bit & 64-Bit)
§ 2.1.The IEEE 754 standard encodes real numbers in normalized scientific notation: (-1)^S × (1.M) × 2^{E - Bias}.
1. Single Precision (32 bits):
- Sign bit (S): 1 bit (0 for positive, 1 for negative).
- Biased Exponent (E): 8 bits. Excess-127 bias (Bias = 127). Normal range: 1 ≤ E ≤ 254. True exponent e = E - 127.
- Mantissa / Significand (M): 23 bits. Represents the fractional part with an implicit leading 1 (1.M).
2. Double Precision (64 bits):
- Sign bit (S): 1 bit.
- Biased Exponent (E): 11 bits. Excess-1023 bias (Bias = 1023). Normal range: 1 ≤ E ≤ 2046. True exponent e = E - 1023.
- Mantissa (M): 52 bits with an implicit leading 1 (1.M).
Special IEEE 754 Encodings & Boundary Cases:
- Zero (+0.0 and -0.0): E = 0, M = 0. Sign bit determines sign.
- Denormalized (Subnormal) Numbers: E = 0, M \ne 0. Value = (-1)^S × (0.M) × 2^{-126} (Single) or 2^{-1022} (Double). Eliminates abrupt underflow!
- Infinity (+∞ and -∞): E = 255 (all 1s), M = 0. Produced on overflow or non-zero division by zero (1.0 / 0.0).
- Not-a-Number (NaN): E = 255 (all 1s), M \ne 0. Represents invalid operations like 0.0 / 0.0 or \sqrt{-1}.
2. GATE Worked Numerical: Encoding Real Decimal to IEEE 754 Hex
Remember that the biased exponent E = e + 127. When normalizing, the radix point moves past the first non-zero bit, leaving an implicit leading 1 that is NOT stored in the mantissa!
Problem: Convert the decimal number -13.625 into IEEE 754 single-precision format and write the 32-bit result in hexadecimal.
Step 1: Sign bit:
Number is negative \implies S = 1.
Step 2: Binary conversion of magnitude 13.625:
Integer part 13 = 1101_2.
Fractional part 0.625 = 0.5 + 0.125 = 2^{-1} + 2^{-3} = 0.101_2.
Combined binary = 1101.101_2.
Step 3: Normalize to 1.M × 2^e:
1101.101_2 = 1.101101_2 × 2^3.
True exponent e = 3.
Mantissa M = 10110100000000000000000 (padded with trailing zeros to 23 bits).
Step 4: Compute biased exponent E:
E = e + Bias = 3 + 127 = 130 = 10000010_2.
Step 5: Assemble the 32-bit field:
[S (1)] [E (8)] [M (23)]
1 10000010 10110100000000000000000
Step 6: Group into 4-bit nibbles for hexadecimal:
1100 0001 0101 1010 0000 0000 0000 0000
Hexadecimal representation = 0xC15A0000.
3.Booth's Multiplication Algorithm for Signed 2's Complement
§ 2.3.Booth's multiplication algorithm multiplies two signed 2's complement integers by exploiting strings of consecutive 1s to reduce additions and subtractions.
Hardware Registers:
- A (Accumulator): Initialized to 0 (n bits).
- Q (Multiplier): Stores the multiplier (n bits).
- Q_{-1} (Extra bit): Initialized to 0 (1 bit).
- M (Multiplicand): Stores the multiplicand (n bits).
Algorithm Execution Cycle (Repeated n times):
At each step, inspect the two least significant bits (Q_0, Q_{-1}):
1. 10: Subtract Multiplicand from Accumulator: A ≤ftarrow A - M. Then perform Arithmetic Right Shift (ARS) on [A, Q, Q_{-1}].
2. 01: Add Multiplicand to Accumulator: A ≤ftarrow A + M. Then perform Arithmetic Right Shift (ARS) on [A, Q, Q_{-1}].
3. 00 or 11: No arithmetic operation; simply perform Arithmetic Right Shift (ARS) on [A, Q, Q_{-1}].
Arithmetic Right Shift (ARS) Invariant:
In ARS, the sign bit (A_{n-1}) is duplicated into itself during the shift: A_{n-1} ≤ftarrow A_{n-1}, preserving the negative sign.
Worst case for Booth's algorithm occurs when bits alternate: 01010101... (requires an addition/subtraction in EVERY step). Best case occurs when the multiplier contains long contiguous runs of 1s or 0s: e.g., 00001111 requires only ONE subtraction at the start and ONE addition at the end!
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