Interrupts, Daisy Chaining Priority & Bus Arbitration
“Vectored vs non-vectored interrupts, daisy chaining propagation delay, and bus arbitration.”
1.Interrupts & Interrupt Service Routine (ISR) Flow
§ 5.1.An Interrupt is an asynchronous signal from hardware (I/O device, timer) or a synchronous trap from software that demands immediate CPU attention.
Interrupt Handling Sequence:
1. CPU checks the interrupt line at the conclusion of the current instruction execution cycle.
2. If an interrupt is asserted and interrupts are enabled: CPU pushes current Program Counter (PC) and processor status register (PSR) onto the hardware stack.
3. CPU issues an Interrupt Acknowledge (INTA) signal.
4. Vectored vs Non-Vectored Interrupts:
- Vectored Interrupt: The interrupting device places an interrupt vector address (or vector number) directly onto the data bus. The CPU branches directly to that specific ISR address in the Interrupt Vector Table (IVT).
- Non-Vectored Interrupt: The CPU branches to a fixed single memory address, where a polling software routine queries each I/O device's status register sequentially to determine the interrupt source.
Priority Interrupt Schemes:
- Software Polling: CPU polls devices in order of descending priority. Slow, latency proportional to the number of devices.
- Hardware Daisy Chaining: Serial priority arbitration. The INTA line passes sequentially through Device 1 \to Device 2 \to Device 3. Device 1 has highest priority. If it requested an interrupt, it blocks INTA from propagating further down the chain.
- Parallel Priority Encoder: All interrupt request lines connect in parallel to a priority encoder hardware chip that outputs the binary code of the highest-priority active device in O(1) gate delays.
2. GATE Worked Numerical: DMA Cycle Stealing CPU Overhead
Data rate must be matched with bus transfer cycle time! Always compute how many bus cycles are stolen per second.
Problem: A hard disk transfers data at a rate of 4 MB/sec (where 1 MB = 10^6 bytes). The system bus has a cycle time of 200 ns and transfers 1 byte per cycle. The CPU clock frequency is 20 MHz with an average CPI of 2.0.
Find the percentage of CPU execution time stolen by the DMA controller in cycle-stealing mode.
Step 1: Bytes transferred per second:
Rate = 4 × 10^6 bytes/second.
Step 2: Time required for one byte transfer over the bus:
T_{bus} = 200 ns = 200 × 10^{-9} s.
Step 3: Total bus time stolen by DMA in 1 second:
Time Stolen = 4 × 10^6 bytes × (200 × 10^{-9} s/byte) = 4 × 10^6 × 2 × 10^{-7} = 0.80 seconds.
Step 4: Percentage of CPU time consumed by DMA:
Percentage = \frac{0.80 s}{1.00 s} × 100% = 80%.
The CPU is slowed down by 80%, retaining only 20% of its normal execution bandwidth.
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