Microprogrammed Control Units & DMA Transfer Modes
“Horizontal/Vertical control words, control store sizing, and DMA cycle stealing.”
1.Control Unit Design: Hardwired vs Microprogrammed
§ 5.1.The Control Unit (CU) orchestrates the processor datapath by generating binary control signals that open multiplexers, enable registers, and command the ALU:
1. Hardwired Control Unit:
- Implemented using fixed combinational logic gates, decoders, and finite state machines.
- Extremely fast clock frequencies (used in RISC architectures).
- Inflexible: Adding or modifying instructions requires physically redesigning the silicon chip layout.
2. Microprogrammed Control Unit:
- Control signals are stored as binary words ('microinstructions') inside an internal fast ROM called Control Memory (CM).
- Highly flexible (used in CISC architectures): instruction set extensions can be implemented by updating ROM firmware.
- Slower execution due to control memory read latency.
Horizontal vs Vertical Microinstruction Architectures:
- Horizontal Microinstruction: Every control signal is allocated a dedicated bit (1 bit per signal). No decoder needed. Wide control word, maximum parallelism, large ROM size.
- Vertical Microinstruction: Mutually exclusive control signals are partitioned into groups and encoded into binary fields. A field of n mutually exclusive signals requires \lceil \log_2(n + 1) \rceil bits (where +1 accounts for the NO-OP / inactive state). Narrow control word, requires external decoders.
2. GATE Worked Numerical: Horizontal vs Vertical Control Word Width
Always include the +1 state for the inactive / NO-OP condition in vertical microinstruction field encoding! A group of 7 signals requires ceil(log2(7 + 1)) = 3 bits.
Problem: A processor has 32 control signals divided into 4 mutually exclusive groups containing 7, 12, 5, and 8 signals respectively. The control memory stores 512 words. Find:
1. Control word bit-width for horizontal microprogramming.
2. Control word bit-width for vertical microprogramming.
3. Total bits saved in the control store.
Step 1: Horizontal control word width:
1 bit per signal \implies 32 bits.
Step 2: Vertical control word encoding for each group:
Group 1 (7 signals): \lceil \log_2(7 + 1) \rceil = \lceil \log_2 8 \rceil = 3 bits.
Group 2 (12 signals): \lceil \log_2(12 + 1) \rceil = \lceil \log_2 13 \rceil = 4 bits.
Group 3 (5 signals): \lceil \log_2(5 + 1) \rceil = \lceil \log_2 6 \rceil = 3 bits.
Group 4 (8 signals): \lceil \log_2(8 + 1) \rceil = \lceil \log_2 9 \rceil = 4 bits.
Total vertical control bits = 3 + 4 + 3 + 4 = 14 bits.
Step 3: Total control memory bit comparison:
Size_{horizontal} = 512 words × 32 bits = 16,384 bits.
Size_{vertical} = 512 words × 14 bits = 7,168 bits.
Bits saved = 16,384 - 7,168 = 9,216 bits (56.25% memory reduction).
3.Direct Memory Access (DMA) & Transfer Modes
§ 5.3.Direct Memory Access (DMA) enables high-speed peripheral devices (disks, network cards) to transfer data directly to/from main memory without continuous CPU intervention.
The Three DMA Operational Modes:
1. Burst Mode (Block Transfer): The DMA controller acquires the system bus and transfers an entire contiguous block of data. The CPU is completely halted from accessing memory during the transfer.
2. Cycle Stealing Mode: The DMA controller 'steals' one bus cycle from the CPU at a time, interleaving memory cycles between CPU execution and DMA transfer. CPU execution is slowed down proportionally, but never blocked.
3. Transparent (Hidden) Mode: The DMA controller transfers data only when the CPU is performing internal operations (such as ALU execution) and is not using the system bus. Zero CPU slowdown!
If a peripheral produces data at rate R bytes/sec, and the memory bus transfers 1 byte in time T_bus, the fraction of CPU time stolen by DMA is: Fraction = R * T_bus. CPU execution is slowed by this exact percentage!
Primary Academic References & Exam Sources
Every concept in Notes From a B.Tech Brain is synthesized from authoritative academic texts, seminal peer-reviewed research, verified exam archives, and renowned university lectures.
Curated for clarity, rigorous numerical solving, and semester excellence:
Rapid GATE-focused conceptual coverage with numericals.
Past-paper-focused approach with clear COA numerical explanations.
Graduate-level depth on how real modern processors are designed.