DIGITAL LOGIC/Student Engineering Notebook
Page 06·notes
COMBINATIONAL LOGIC MODULES & CIRCUIT SYNTHESIS—~28 MIN READ

Decoders, Encoders, Priority Encoders & Code Converters

“Active-low minterm generators, priority resolution truth tables, and BCD-to-seven-segment logic.”

1.Decoders and Priority Encoders in Hardware Architecture

A Decoder is a combinational circuit that converts an n-bit binary input code into 2^n unique output lines. Exactly one output line is activated for each input combination.

Minterm Generator: Because each output corresponds to a specific minterm, any Boolean function expressed in canonical SOP form f = \sum m(1, 3, 7) can be synthesized simply by feeding the corresponding decoder outputs into an OR gate.

Active-Low Decoders: Most real TTL/CMOS decoders use active-low outputs (Y_i = 0 when selected, 1 otherwise). By De Morgan's laws: \sum m_i = (\prod m_i')' = (\prod Y_i)'. Therefore, connecting active-low decoder outputs to a NAND gate directly produces the OR of minterms!

Priority Encoders: Standard encoders assume exactly one input is active at any time. When multiple inputs are asserted simultaneously (as in hardware interrupt controllers), a standard encoder produces corrupted outputs. A Priority Encoder guarantees that the output reflects the index of the highest-priority asserted request.

WORKED EXAM ANALYSIS · STEP-BY-STEP DERIVATION2 Marks (GATE CS)

2. Worked Analysis: Logic Function Synthesis via Active-Low Decoder

⚠️ Pitfall Warning:

Active-low outputs combined into a NOR or AND gate perform different dual functions.

Problem Statement (Modeled on GATE Pattern):

A 3-to-8 decoder has active-low outputs Y0' through Y7' where Y_k' = 0 iff input (A, B, C) represents binary k.

The outputs Y1', Y3', Y5', and Y7' are connected to the inputs of an active-low input NAND gate (which is equivalent to an OR gate).

What Boolean function f(A, B, C) is realized?

Step 1: Write output expression of the NAND gate:

f = (Y1' Y3' Y5' * Y7')'.

Step 2: Apply De Morgan's theorem:

f = (Y1')' + (Y3')' + (Y5')' + (Y7')'.

Step 3: Relate to minterms:

Since Y_k' = (m_k)', we have (Y_k')' = m_k.

Therefore, f = m1 + m3 + m5 + m7.

Step 4: Minimize the minterm sum:

m1 = A'B'C, m3 = A'BC, m5 = AB'C, m7 = ABC.

Factor out C: f = (A'B' + A'B + AB' + AB) C = 1 * C = C.

Result: The circuit computes the simple identity f(A, B, C) = C.

SOURCE TRANSPARENCY & CITATIONS

Primary Academic References & Exam Sources

Every concept in Notes From a B.Tech Brain is synthesized from authoritative academic texts, seminal peer-reviewed research, verified exam archives, and renowned university lectures.

Curated University Lecture Series
Digital Design: With an Introduction to the Verilog HDL ·
LECTURE SERIES
RECOMMENDED YOUTUBE EDUCATORS & FULL-COURSE PLAYLISTS

Curated for clarity, rigorous numerical solving, and semester excellence:

Neso Academy · Digital Electronics Full Course↗Instructor: Neso Academy · Covers: Boolean algebra, K-maps, combinational circuits, flip-flops, sequential logic

The most thorough digital logic series — textbook quality at no cost.

Open YouTube↗
Gate Smashers · Digital Logic for GATE↗Instructor: Varun Singla · Covers: K-map minimization, multiplexers, decoders, flip-flop conversions, counters

GATE-focused digital logic with exam-style numericals.

Open YouTube↗