DIGITAL LOGIC/Student Engineering Notebook
Page 05·notes
COMBINATIONAL LOGIC MODULES & CIRCUIT SYNTHESIS—~30 MIN READ

Multiplexers, Shannon's Expansion & Universal Logic Synthesis

“2^n:1 MUX synthesis, tree expansions, Shannon's decomposition, and universal logic generation.”

1.The Universal Logic of Multiplexers

A Multiplexer (MUX) is a combinational selector that routes one of 2^n data inputs to a single output based on n select lines.

Why Multiplexers are Universal: Multiplexers are fundamentally hardware implementations of truth tables. By connecting variables to select lines, each data input I_i corresponds to a specific row (or pair of rows) of the truth table.

Synthesis Strategies:

1. n-variable function with 2^n:1 MUX: Connect all n variables to the select lines. Connect I_i = 1 if minterm m_i is in the function, and I_i = 0 otherwise.

2. (n+1)-variable function with 2^n:1 MUX: Connect n variables to the select lines. For each combination of the select variables, express the output as a function of the remaining single variable C. The value of each I_i will be one of: 0, 1, C, or C'.

3. Modular Expansion: To construct a 2^n:1 MUX using 2^k:1 MUXes (k < n), the total number of smaller multiplexers required is given by the geometric series: \sum_{i=1}^{\lceil n/k \rceil} \frac{2^n}{2^{k \cdot i}}. Specifically, to build a 2^n:1 MUX entirely from 2:1 MUXes requires exactly 2^n - 1 modules.

mental model— Tree Architecture Calculation

Building a 64:1 MUX from 4:1 MUXes requires: Stage 1 = 64/4 = 16 MUXes; Stage 2 = 16/4 = 4 MUXes; Stage 3 = 4/4 = 1 MUX. Total = 16 + 4 + 1 = 21 MUXes.

WORKED EXAM ANALYSIS · STEP-BY-STEP DERIVATION2 Marks (GATE CS)

2. Worked Analysis: Function Synthesis via 4:1 MUX with Reordered Select Lines

⚠️ Pitfall Warning:

Notice that select inputs are chosen as B (MSB) and C (LSB), leaving A as the input data variable.

Problem Statement (Modeled on GATE Pattern):

Implement the function f(A, B, C) = Sigma m(0, 1, 4, 6, 7) using a 4:1 MUX where select lines are connected as S1 = B and S0 = C.

Determine the inputs (I0, I1, I2, I3) connected to data lines.

Step 1: Write truth table grouped by select lines (B, C):

For BC = 00 (I0): covers m0 (A=0, BC=00) and m4 (A=1, BC=00).

Both m0 and m4 are present in f! Thus, when BC = 00, f = 1 regardless of A.

Therefore, I0 = 1.

For BC = 01 (I1): covers m1 (A=0, BC=01) and m5 (A=1, BC=01).

m1 is in f (output 1), m5 is NOT in f (output 0).

When A = 0, f = 1; when A = 1, f = 0 -> f = A'.

Therefore, I1 = A'.

For BC = 10 (I2): covers m2 (A=0, BC=10) and m6 (A=1, BC=10).

m2 is NOT in f (output 0), m6 is in f (output 1).

When A = 0, f = 0; when A = 1, f = 1 -> f = A.

Therefore, I2 = A.

For BC = 11 (I3): covers m3 (A=0, BC=11) and m7 (A=1, BC=11).

m3 is NOT in f (output 0), m7 is in f (output 1).

When A = 0, f = 0; when A = 1, f = 1 -> f = A.

Therefore, I3 = A.

Result: The data inputs are (I0, I1, I2, I3) = (1, A', A, A).

SOURCE TRANSPARENCY & CITATIONS

Primary Academic References & Exam Sources

Every concept in Notes From a B.Tech Brain is synthesized from authoritative academic texts, seminal peer-reviewed research, verified exam archives, and renowned university lectures.

Curated University Lecture Series
Fundamentals of Logic Design (7th Edition) ·
LECTURE SERIES
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