Digital Logic
“Master Boolean algebra, K-Maps, multiplexer implementations, flip-flop timing, counters, and finite state machines.”
A comprehensive, hardware-foundational study notebook covering Boolean algebra, canonical representations, combinational circuit synthesis, number representations, arithmetic units, sequential machines, and timing constraints for university examinations and GATE CS/IT.
Structured Notes & Exam Lens
A · B.Tech Structured Study Sequence
5 Sections · Full CurriculumBoolean Algebra, Canonical Forms & K-Map Minimization
Boolean axioms, De Morgan's laws, consensus theorem, duality, canonical SOP/POS expressions, prime implicants, essential prime implicants, and K-map minimization.
Hunting algebraic redundancies, Shannon's expansion theorem, duality rules, and self-dual function counts.
Gray code adjacency, essential prime implicants, minimal SOP/POS, and 5-variable K-map partitions.
Number Representation & Computer Arithmetic Circuits
Signed magnitude, 1's and 2's complement arithmetic, range formulas, overflow conditions, half adders, full adders, ripple carry adders, and carry lookahead adders.
Range boundaries, sign extension rules, modular arithmetic, and two's complement overflow detection.
Gate propagation delays, Half/Full adder synthesis, CLA generate and propagate algebra, and asymptotic speedup.
Combinational Logic Modules & Circuit Synthesis
Multiplexers, Shannon's expansion, decoders with active-low enables, priority encoders, magnitude comparators, and programmable logic architectures (PROM, PLA, PAL).
2^n:1 MUX synthesis, tree expansions, Shannon's decomposition, and universal logic generation.
Active-low minterm generators, priority resolution truth tables, and BCD-to-seven-segment logic.
Cascaded comparator delays, even/odd parity generation, and architectural differences between PROM, PLA, and PAL.
Sequential Circuits, Latches & Flip-Flop Dynamics
Latches vs Flip-flops, characteristic equations, excitation tables, conversion methodology, race-around condition, and synchronous/asynchronous counter synthesis.
Master-slave architectures, excitation tables, characteristic equations, and flip-flop conversion algorithms.
Ripple counter glitch hazards, synchronous state table synthesis, unused states, and self-correcting counters.
Shift Registers, Finite State Machines & Timing Constraints
SISO, SIPO, PISO, PIPO shift registers, Mealy vs Moore state machines, state minimization, setup time, hold time, clock skew, and maximum operating frequency.
Mealy vs Moore machines, setup and hold slack inequalities, clock skew hazards, and metastabiliy.
B · GATE 2027 Syllabus Scope
Official syllabus scope and related lesson coverage; topics outside the syllabus are marked as enrichment.
- •Boolean algebra: Combinational and sequential circuits, minimization, number representations and computer arithmetic
- •Combinational circuits: Multiplexers, decoders, encoders, priority encoders, adders, subtractors, comparators, PLAs, PALs
- •Sequential circuits: Latches, flip-flops, synchronous and asynchronous counters, shift registers, state machines, setup and hold time
Interactive Labs & Verified PYQs
Revision & Rapid Review Sheets
Authoritative Textbooks & Video Lectures
All notes in this notebook cross-reference standard academic literature. We do not pretend student notes substitute for classical texts — they guide you through them.
Curated lectures from verified educators (Gate Smashers, Neso Academy, Knowledge Gate, and MIT OCW) selected specifically for difficult concept visualizations.
These notes are open and maintained together.
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